Kerniv / Autonomous hardware validation

Intelligence for Real-World Engineering.

The AI validation engineer for physical hardware.

Kerniv is building an intelligent engineering platform that understands electronic designs, operates real test equipment, investigates hardware and firmware failures, and turns measurements into reproducible engineering evidence.

Early stage · design partners welcome

  • Engineering evidence, not AI confidence
  • Deterministic safety limits
  • Engineers keep final sign-off

The gap

AI can generate the design. Who verifies the hardware?

Software engineering automated its verification years ago: every change runs against deterministic checks before anyone trusts it. Physical engineering still depends on manual laboratory work — configure, measure, export, interpret, repeat — and on the experience of the engineer holding the probe.

A validation engineer’s evidence lives across:

  • Schematics
  • PCB layouts
  • Firmware repos
  • Datasheets
  • Requirements
  • Oscilloscopes
  • Logic analyzers
  • Power supplies
  • Electronic loads
  • HIL rigs
  • Lab logs
  • Spreadsheets

The bottleneck is not collecting more data. It is connecting engineering intent with physical behavior.

Traditional hardware validation

Manual · serial effort
  1. 01 Configure each instrument by hand for every run
  2. 02 Execute the test and capture waveforms
  3. 03 Export the measurements and note the test conditions
  4. 04 Interpret the results and search for likely causes
  5. 05 Modify firmware or parameters and run it again
  6. 06 Repeat until the behavior is explained

Slow to start, hard to repeat, and dependent on whoever remembers the conditions of the last run.

Kerniv’s intended workflow

Platform vision
  1. 01 Interpret the requirements, schematics and firmware
  2. 02 Prepare experiments inside pre-approved limits
  3. 03 Coordinate instrument actions through typed interfaces
  4. 04 Grade measurements against written acceptance criteria
  5. 05 Propose candidate failure mechanisms, not conclusions
  6. 06 Produce a traceable record with the next experiment attached

Every experiment leaves a record: configuration, limits, measurement references and the reasoning that selected it.

Kerniv extends engineering capacity and removes repetitive diagnostic effort. It does not remove engineers from the loop — judgment, safety and sign-off stay with people.

Platform

From engineering intent to physical evidence.

Kerniv closes the loop between what a design is meant to do and what the hardware actually does. Reasoning selects and configures experiments; instruments execute them; measurements are graded against written acceptance criteria; and every result returns to the reasoning layer as new context.

  1. 01

    Engineering context

    Defines intent

    What the hardware is supposed to do, and how it was meant to do it.

    • Schematics
    • PCB layouts
    • Component datasheets
    • Firmware & source
    • Engineering requirements
    • Simulation models
    • Historical test results
  2. 02

    Engineering intelligence

    Emerging capability

    Reasoning over design intent: what to test, what failed, what to try next.

    • Circuit topology interpretation
    • Constraint extraction
    • Test planning
    • Hypothesis generation
    • Fault localization
    • Experiment selection
    • Evidence-based diagnosis
  3. 03

    Instrument orchestration

    Existing lab equipment

    Approved actions on the equipment your lab already runs.

    • Oscilloscopes
    • Programmable supplies
    • Electronic loads
    • Digital multimeters
    • Logic analyzers
    • CAN & comms interfaces
    • Firmware debug probes
    • DAQ & HIL environments
  4. 04

    Physical system

    Device under test

    The hardware whose behavior decides whether the design is right.

    • DC/DC converters
    • Motor controllers
    • Robotic actuators
    • Embedded controllers
    • Electronic subsystems
  5. 05

    Verification & evidence

    Evidence out

    Results a review can stand on — and re-run.

    • Measured results
    • Test verdicts
    • Diagnostic hypotheses
    • Failure classifications
    • Reproducible experiment records
    • Regression tests
    • Engineering review material

Platform vision Kerniv is in early development. The diagram describes the intended system; specific capabilities are scoped and validated with design partners rather than assumed shipped.

How it works

A hardware failure. Investigated by intelligence.

See how Kerniv could transform electrical measurements into a structured diagnostic investigation — using a low-voltage DC/DC converter and a load-transient failure as the worked example.

KNV-PWR-0142 Sync buck converter — 24 V in, 12 V / 3 A out Illustrative engineering workflow
Step 01 / 07

01 Understand the design

The system receives the converter schematic, firmware information and the engineering requirements, and resolves the circuit into functional blocks.

24 V H L SW 10 µH 220 µF FB load buck controller 1 2 3 4 5 6 7
  • 1 Input & supply 24 V nominal, 9–36 V operating range
  • 2 Controller Synchronous buck controller, external compensation
  • 3 Switching stage High-side / low-side MOSFET pair, 500 kHz nominal
  • 4 Inductor L = 10 µH, 6 A saturation
  • 5 Output capacitance C = 220 µF effective, low-ESR
  • 6 Feedback network Resistive divider to the controller FB pin
  • 7 Load Programmable electronic load, 0–5 A

02 Define expected behavior

The requirements resolve into an executable load-transient test: a written pass/fail definition exists before any instrument is touched.

Regulation at steady state
12.0 V ±1 %
Transient deviation
±3 % (11.64 – 12.36 V)
Recovery to ±1 %
≤ 500 µs
Output ripple
≤ 50 mVpp
Load step
0.5 A → 3 A, 1 A/µs, at VIN = 24 V
12.36 V  +3 % 11.64 V  −3 % 12.00 V nom acceptance window during transient

03 Execute the measurement

Approved instrument actions execute the test. Output voltage, load current and the switching node are captured on one timebase.

load step 11.011.411.812.212.6 0.01.53.0 0.00.51.01.52.02.53.0 V_OUT / V I_LOAD / A SW time / ms 11.31 V · −5.75 %
  • VOUT min11.31 V
  • Undershoot−5.75 %
  • Recovery ±1 %1.2 ms
  • Ring≈ 1.3 kHz

04 Identify the deviation

Measurements are graded against the written acceptance criteria — deterministically, without a model in the decision path.

  • Steady-state regulation 12.02 V (12.0 V ±1 %) Pass
  • Transient deviation −5.75 % (limit ±3 %) Fail
  • Recovery to ±1 % 1.2 ms (limit 0.5 ms) Fail
  • Output ripple 34 mV (limit 50 mV) Pass

Transient response outside acceptance — investigation opened

The deviation is measured evidence. The root cause is not yet established; the next steps exist to rank candidate explanations.

05 Investigate possible causes

Candidate failure mechanisms are ranked against the measured signatures. These are hypotheses with stated support — not conclusions.

  • Control-loop compensation

    Leading candidate

    Consistent with the observed ≈ 1.3 kHz ring and the slow return toward regulation. An under-damped loop explains both signatures without additional assumptions.

    Discriminating test Ring frequency should be invariant to V_IN but shift with load capacitance.

  • Feedback sense-network lag

    Plausible

    A slow or heavily filtered feedback path reduces effective loop bandwidth and produces the same class of response. Cannot be separated from compensation with the current data.

    Discriminating test Sweep the sense filter corner and watch the ring frequency.

  • Input supply droop

    Requires measurement

    V_IN was not recorded during this run. A sagging input under step load would deepen the undershoot, but there is no evidence either way yet.

    Discriminating test Repeat the step while recording V_IN at the converter terminals.

  • Current-limit foldback

    Not supported

    A current-limit event produces a flat-topped, hysteretic response. The measured recovery is smooth and oscillatory, which argues against this mechanism.

    Discriminating test Deprioritized — no servicing evidence.

06 Recommend the next experiment

The system selects one additional test that can separate the leading explanations — inside a pre-approved electrical envelope.

If the ring frequency tracks V_IN, supply impedance moves up the ranking. If it is invariant to V_IN but shifts with the sense filter, the feedback path dominates. Only then is a compensation change justified.

07 Create engineering evidence

Everything above becomes one reviewable record: configuration, evidence, candidates and the open question.

Test ID
KNV-PWR-0142 · load-transient response
DUT
Sync buck converter — 24 V in, 12 V / 3 A out
Configuration
Programmable DC supply (SCPI) · electronic load (SCPI) · 4-channel oscilloscope (SCPI) · 100 MS/s, 3 ms window
Conditions
V_IN = 24 V · ambient 23.4 °C · fw-0e12a7c
Observed deviation
−5.75 % undershoot (11.31 V min) · recovery 1.2 ms · ring ≈ 1.3 kHz
Candidate explanations
Control-loop compensation (leading) · feedback sense lag · input droop (unmeasured) · current foldback (not supported)
Next recommended test
Load-step sweep at three input voltages with sense-path variation — pending operator approval
Human review
PENDING — no conclusion is released without an engineer’s sign-off
Generated in your browser from the sample data above.
Sample data · deterministic · no external AI calls Human sign-off required for any conclusion

Applications

Built for systems that interact with reality.

Kerniv’s initial focus is the electronics that convert, control and protect power. The verification loop — intent, experiment, measurement, evidence — is designed to extend to adjacent systems as the platform matures.

Power electronics

Initial focus

Automating characterization, control-system investigation, protection testing and validation of converters and power stages.

  • DC/DC converters
  • Gate-driver behavior
  • Power-stage startup
  • Load-transient response
  • Current sensing
  • Converter protection

Robotics & motor control

Focus area

Electrical validation for the systems behind motion and actuation — from inverter switching to current-loop behavior.

  • Motor inverters
  • Servo drives
  • Actuator controllers
  • Current-loop behavior
  • Encoder & sensor interfaces
  • Embedded motion control

Embedded systems

Focus area

Connecting firmware debugging with observed physical behavior, so timing and integration defects surface as measurements.

  • Peripheral interfaces
  • Hardware–software integration
  • Boot & startup behavior
  • Timing-related defects
  • Regression testing
  • Device communication

Advanced power infrastructure

Future direction

Longer-range applicability to demanding conversion and protection systems, including power delivery for AI computing infrastructure.

  • High-density converters
  • Power distribution electronics
  • Power protection
  • Industrial power systems
  • AI computing infrastructure

Initial commercial focus: power converters, motor controllers and embedded control systems. Infrastructure applications describe intended future scope, not current product support.

Principles

Intelligence proposes. Engineering verifies.

These are design commitments, not aspirations. They are what keep an ambitious system honest in front of a real board, a real instrument and a real reviewer.

  1. 01

    Evidence over confidence

    A plausible AI answer is not a test result. Verification outcomes come from measurements and objective acceptance criteria — never from how certain a model sounds.

  2. 02

    Deterministic safety boundaries

    Agents cannot change voltage limits, disable protection systems, bypass interlocks, or declare unsafe operations acceptable. Safety-critical control lives in deterministic code, bounded by equipment capabilities and approved by qualified engineers.

  3. 03

    Traceable decisions

    Every engineering result connects to its inputs, instrument settings, test conditions, execution history and the reasoning that selected it — so any conclusion can be reconstructed, not merely believed.

  4. 04

    Engineers remain in control

    Engineering professionals define objectives, approve high-risk actions, interpret uncertainty and hold final sign-off. The platform is designed around that division of responsibility, not in spite of it.

  5. 05

    Hardware-independent intelligence

    Kerniv is intended to integrate with established measurement equipment and commodity computing. Its value is engineering reasoning and orchestration — not a walled garden of instruments.

Architecture

Built for the laboratory. Designed for intelligence.

The platform is layered so that reasoning and verification never blur together. Each stage has one job, and the boundary between them is enforced in code.

  1. 01 Engineering context
  2. 02 AI engineering runtime
  3. 03 Deterministic execution & verification
  4. 04 Instrumentation interfaces
  5. 05 Physical hardware
  6. 06 Evidence & results

Evidence returns to the runtime as new context — every experiment informs the next one.

The determinism boundary

The model proposes. Code disposes.

The runtime proposes typed tool calls. A deterministic execution layer validates every call against pre-approved envelopes — voltage, current, timing, sequence — before anything reaches an instrument. Independent verifiers grade results against written criteria.

Model output never commands hardware directly, and an agent cannot certify its own work.

Instrumentation interfaces
  • SCPI
  • VISA
  • Python APIs
  • LAN / USB / GPIB
  • DAQ
  • HIL
  • SWD / JTAG debug

Integration with existing laboratory equipment comes first. A dedicated Kerniv acquisition device is a possible future product — not a prerequisite for working with the platform.

Computing architecture

Intelligence is intended to run on commodity compute where practical: standard workstations, professional GPUs, local or appropriately secured model inference, and the computers your lab already owns.

Precise measurement timing, triggering, high-speed acquisition and protection may require dedicated FPGA, microcontroller or instrument hardware. The split is deliberate: reasoning on general compute, determinism on dedicated silicon.

Design partners

Help define the next generation of hardware validation.

Kerniv is seeking engineering teams willing to explore a new approach to physical hardware testing, debugging and validation. We are especially interested in organizations developing power converters, motor controllers, robotic systems and complex embedded electronics.

What an engagement involves

  1. 01

    Discover

    Understand one recurring validation challenge and the manual workflow it lives in today.

  2. 02

    Establish a baseline

    Define success criteria, safety constraints and the engineering effort the task currently costs.

  3. 03

    Integrate

    Connect the relevant documents, software and test instruments — within agreed data controls.

  4. 04

    Demonstrate

    Develop a bounded validation workflow and measure its performance against the baseline.

  5. 05

    Evaluate

    Review results, limitations and next steps together. We would rather say no early than oversell.

Prefer email? Write directly to hello@kerniv.com — replies come from an engineer, usually within two business days.

Apply as a design partner

Opens your email client with the details pre-filled. Nothing is stored on this page; nothing you send is used to train a model.

About Kerniv

Domain expertise before ambition.

Kerniv is founded by an engineer with a doctorate in electrical engineering focused on power electronics and electrical machines. That background spans automotive electronics, converter systems, embedded hardware, technical leadership and hardware validation — the unglamorous work of proving a design survives its operating conditions.

The company exists because the hardest part of hardware engineering is not generating designs. It is producing evidence that they work. Kerniv applies AI where its output can be verified, and keeps people where judgment, safety and liability matter.

Working on a validation problem worth solving? Start a conversation or write to hello@kerniv.com.

Questions

The ones worth asking.

If yours is not here, ask directly — we would rather answer the hard question early than discover it in week four.

Ask us something
What is Kerniv?

Kerniv is building an AI-based engineering platform focused on hardware testing, validation and diagnosis. It connects engineering reasoning with real measurement instruments, so design hypotheses can be tested against physical behavior rather than plausible-sounding text.

Does Kerniv replace engineers?

No. Kerniv aims to automate repeatable engineering tasks and support investigation. Engineers retain responsibility for objectives, safety, interpretation of uncertainty and final decisions. If anything, the platform raises the value of experienced judgment.

Do we need to purchase new test equipment?

The intended architecture prioritizes integration with existing instruments wherever technically feasible. Actual compatibility depends on the specific device and the scope of integration, and is established case by case during design-partner work.

Can Kerniv work with our firmware and schematics?

Understanding electrical designs, embedded software and engineering requirements is central to the platform vision. Which formats and toolchains are supported first will be determined during development and design-partner engagements — not promised in advance.

Is Kerniv available today?

Kerniv is in an early development and design-partner stage. Specific available capabilities, integration scope and limitations are confirmed during the initial discussion, so nobody is working from marketing claims.

How is sensitive engineering data handled?

Confidentiality and data control are design requirements, not afterthoughts. Actual storage, retention, hosting and security arrangements are defined and agreed in writing before any customer integration begins.

What about safety-critical test equipment?

Autonomous execution must be constrained by deterministic safety mechanisms, equipment capabilities and appropriate human approval. Kerniv does not let language models command instruments outside pre-approved electrical and operational envelopes.